1. Field of the Invention
This invention generally relates to a semiconductor device, and, in particular, to a semiconductor memory device. More specifically, the present invention relates to a sense circuit for use in a semiconductor memory device, such as a read only memory or simply ROM, and to a MOS transistor suitable for use in a semiconductor memory device.
2. Description of the Prior Art
A semiconductor memory device, such as a ROM, is well known in the art. In a ROM, typically, two levels of current, I.sub.1 and I.sub.2, flow through a memory cell, and it is necessary to determine which level of current flows through a selected one of memory cells arranged in the form of a matrix. In order to determine the level of current flowing through a selected memory cell, there is typically provided a reference cell, through which current having the level of approximately (I.sub.1 +I.sub.2)/2 flows, and this current level is compared with the current level of the selected memory cell. In this case, it is required to create two different states for a memory cell and one state for the reference cell, so that the total number of states required is three.
FIG. 3 shows a prior art example for the case in which a memory can take one of four states as disclosed in IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 2, pp 598-602, April 1985, which is hereby incorporated by reference. As shown in FIG. 3, there is provided a memory cell M1 which can take one of four states different in level. In other words, under a predetermined bias condition, the level of current flowing through the memory cell M1 is one of four different cases, i.e., I.sub.1, I.sub.2, I.sub.3 and I.sub.4 with the current level increasing gradually in the order as mentioned. Also provided are reference memory cells R1 through R3 and bias circuits 2-1 through 2-4 which provide the same bias condition to the memory cell M1 and the reference cells R1 through R3. It is structured so that the level of current flowing through the reference cell R1 is set between I.sub.1 and I.sub.2, the level of current flowing through the reference cell R2 is set between I.sub.2 and I.sub. 3 and the level of current flowing through the reference cell R3 is set between I.sub.3 and I.sub.4.
The structure shown in FIG. 3 also includes three sense amps 4-1 through 4-3, each of which is connected to compare the drain voltage of the memory cell M1 and the drain voltage of each of the corresponding reference cells R1 through R3 so as to detect the state of the memory cell M1. In this prior art structure, it is required to create three states for each of the reference cells R1 through R3 in order to determine the state of the memory cell M1 in addition to the four states for the memory cell M1. In general, if it is desired to detect one of a number of possible states of a memory cell, it is required to create (n-1) number of states for the reference cells. As a result, in total, it is typically required to create (2n-1) number of states in a memory device. Accordingly, such a requirement would provide an undue difficulty in manufacturing a memory device and manufacture of a memory device can be done only with a low yield.